1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a construction for improving reliability of write and read data of a phase change memory including memory cells each having a data storing element which selectively attains a crystalline state (polycrystalline state) and an amorphous state in accordance with stored data.
2. Description of the Background Art
Nonvolatile memories storing information in a nonvolatile manner have been widely employed in application of portable equipment and others. As such nonvolatile memories, there are a flash memory storing information by storing charges on a floating gate of a stacked gate transistor, and a memory utilizing a resistance value change type memory cell having a resistance value of a memory element changed according to stored information. As the resistance value change type memories, there are known various memories such as a Magnetic RAM (MRAM) utilizing a magnetic resistance effect, a Resistance RAM (RRAM) utilizing changes in resistance of perovskite oxide caused by voltage pulse stimulation, and a Phase Change Memory (PCM) utilizing, as a storage element, a phase change material that changes between a crystalline state (polycrystalline state) and an amorphous state depending on heat treatment, and assumes different resistance values for the respective states.
A prior art reference 1 (Japanese Patent Laying-Open No. 2003-298013) discloses a structure implementing shrunk cells through use of a Sb—Te film as a main component instead of a GST film (Ge—Sb—Te film) with Sb doped by 56% or more, to attain a resistivity of 100 Ωcm for lowering a resistance of a phase change material element in the phase change memory. This prior art reference 1 also discloses that In, Ag and Ge may be added in total at an atomic rate of 15% or lower.
A prior art reference 2 (Japanese Patent Laying-Open No. 2004-186553) discloses a configuration of an RRAM in which source lines are provided in parallel to word lines, and a source line is shared between memory cells arranged in a direction perpendicular to a bit line. In the prior art reference 2, an access transistor is arranged in common to two adjacent variable resistance elements in a row direction, and the access transistor has a large gate width to have a reduced on-resistance: Additionally, this prior art reference 2 shows a construction of a unit cell for which the source line is provided parallel to the bit line.
In the structure disclosed in the foregoing prior art reference 1, the material composition of the phase change material element is selected so as to reduce the resistance value of the phase change material element. According to the prior art reference 1, the resistance value changes between the order of 10 Ω and the order of 10 KΩ corresponding to the crystallized state (crystalline or polycrystalline state) and the amorphous state. Normally, the memory cells storing data according to the resistance values have resistance values varied due to variations in parameters during manufacturing process. In particular, the variation in resistance value is remarkably large in using the phase change material elements, because the amorphous state is utilized for storing information. The prior art reference 1 has given no consideration to the problem related to such variation in resistance value.
Usually, the phase change memory internally reads concurrently the data of multiple bits of the memory cells. When the source line is shared between the memory cells from which the data are concurrently read, read currents flow in parallel through these selected memory cells, and may cause mutual interference between the selected memory cells through the shared source line, so that accurate reading may be difficult. For example, when a plurality of memory cells are connected to a common source line, the memory cell having the lowest resistance value causes a large current to flow through the common source line. When the large current raises the source line potential, the raised potential restricts the read currents of the other selected memory cells, which causes a problem of increase in access time or occurrence of erroneous reading.
As disclosed also in the prior art reference 1, a data write is performed by causing a current to flow through a storage element for changing the crystalline state to the amorphous state, and this writing current flows through the same current path as that for data reading, but is greater by one order or more of magnitude than the current for data reading. Accordingly, a read current path is associated with a stray capacitance of write circuitry for supplying the large write current, resulting in a problem that read current can not be changed fast.
The prior art reference 2 discloses a construction, in which the resistance elements sharing an access transistor are set to low and high resistance states, respectively, to provide a complementary bit line structure, and a sense amplifier senses complementary data for achieving fast data reading. In this construction, however, two variable resistance elements store data of one bit, so that a storage capacity is small.
Instead of the complementary bit line structure, such a structure may be considered that a selected memory cell is coupled to the sense amplifier, and a reference data (current) for the selected memory cell is supplied to this sense amplifier. In this configuration, a reference cell having substantially the same structure as a normal memory cell is utilized as an element for producing a reference current, and this reference cell produces a current corresponding to a resistance value state intermediate between the high and low resistance states. In this configuration, currents are supplied to the normal memory cell and the reference cell while charging a parasitic resistance and a parasitic capacitance present on the data line. Therefore, even during the charging, a current difference between the normal memory cell and the reference cell can be read, so that data can be read fast. In this case, with the use of a cell the same in structure and form as the normal memory cell for the reference cell, temperature characteristics and others can be made identical, to cancel current changes due to operation environments, so that there is no need for providing a characteristic compensating circuit to the read circuit, and the read circuit can be made simple.
Generally, the reference cells are aligned to the normal memory cells, and the normal memory cell and the reference cell on the same row are selected to connect a normal memory cell bit line and a reference cell bit line to the sense amplifier. Therefore, the reference cells are selected more times than the normal memory cells. Since the read current flows through the reference cell, this read current may cause read disturbance, that the state of the phase change material element slowly changes from the amorphous state to the crystalline state, leading to a problem that an accurate reference current cannot be produced.
In the prior art reference 2 described above, consideration is given merely to the construction for reducing the on-resistance of the access transistor in the memory cell, and no consideration is given to the construction of the read unit that produces the reference current by using the reference cell in the high resistance state.
In the data read operation, the read current is supplied to a selected memory cell for determining the resistance value of the selected memory cell, and the read operation is performed through comparison of the memory cell current with the reference voltage or reference current. The current path of the read current supplied to the selected memory cell extends from the sense amplifier (read circuit) through an internal data line, a column (bit line) select gate, a bit line, a memory cell select transistor, a memory cell resistance (phase change material element) and a source line to a ground potential (reference potential source), for example. In this current path, when the lengths of the internal data line, the bit line and the source line change depending on the position of the selected address, i.e. position of the selected memory cell in the memory cell array, the total resistance value of the read current path changes and accordingly, the read current changes. Consequently, a problem arises that a margin for the sense operation in data reading lowers, and accordingly, fast reading of accurate data cannot be achieved.
In the data write operation, a write current path is likewise formed for conducting a write current to the selected memory cell. This write current path is such a route from a write current source through an internal data line, a column select gate, a bit line, a memory cell select transistor, a memory cell (phase change material element) and a source line to a ground potential. In this case, therefore, when the lengths of the internal data line, bit line and source line included in the write current path change depending on the selected address position, the total resistance value of the write current path changes to change the write current value, which results in a problem that a margin in the data write operation is impaired and data writing cannot be performed fast.
When data reading is performed on a multi-bit basis, the data writing is likewise performed to memory cells on a multi-bit basis. When the memory cells selected concurrently share a source line, mutual interference occurs between the selected memory cells via the shared, common source line in the write operation similarly to the read operation. For example, a large write current flows to the shared source line via the memory cell of the smallest resistance value, to raise the potential on the shared source line to restrict the write currents of other memory cells, resulting in an erroneous data writing or others. Further, the write current needs to be large, but a sufficiently large write current cannot flow due to the electric resistance of the shared source line, which may cause erroneous writing.
The prior art reference 2 already described gives no consideration to the problem of changes in source potential on the shared source line during writing or reading. Further, no consideration is given to the problem of changes in read and write currents depending on the position of a selected memory cell in a memory cell array.